1. Field of the Invention
The present invention relates to memories.
2. Description of the Related Art
At present, distinction is essentially made between three types of industrial memory-effect devices integrated on silicon.
Arrays of the DRAM type, that is to say dynamic random access memories, make it possible to read and write individually from and to each of the elementary cells of which they are made up. These dynamic random access memory cells are compact since they are formed by one transistor and one capacitor. They are furthermore quite fast in terms of access time (typically of the order of 40 to 70 nanoseconds) but require frequent refreshing of the information contained in the capacitor of the cell, essentially because of junction leaks of the transistor of the cell.
There are also SRAM arrays, that is to say static random access memory arrays. Static random access memory cells are individually addressable, have short cycle times (access time of from 6 to 70 nanoseconds) and retain the information for as long as they are supplied with power. These memory cells remain handicapped by their low density, however, since a cell is generally made up of 6 transistors.
So-called non-volatile memories are also known (for example so-called “flash” memories) which can retain information for several years inside a floating zone insulated by oxide, and without refreshing or supplying power. These memories are compact since they are formed by a single transistor, but the mechanism of writing by the tunnel effect through the insulation oxide of the floating zone is slow and requires strong biases, with access times that can vary from of the order of a microsecond up to a millisecond. Furthermore, these cells are not individually addressable when erasing.
U.S. Pat. No. 5,633,178 furthermore discloses a non-volatile memory cell formed by a single insulated-gate transistor whose gate oxide contains electron traps, which are arranged in contact with the substrate. The writing of a logical “1” or a logical “0” into the memory cell is carried out by vertical movement of charges so as either to fill the electron traps or to empty them. The localization of electron traps at the interface between the gate dielectric and the substrate is particularly difficult to control from a technological point of view.
U.S. Pat. No. 6,128,243 furthermore discloses a tunnel-junction memory (TJM memory) cell containing crystals of semiconductor material in the gate oxide of the transistor constituting this cell. Such a cell is used as a backup cell to provide a medium for holding the information of an SRAM memory during a possible power cut. Furthermore, the mechanism of storing charges in this prior art cell relies on vertical transfer of the charges from the channel to the crystals. Writing is then carried out with hot electrons or with a tunnel current, and erasing is carried out with a tunnel current.
Accordingly, there exists a need for overcoming the disadvantages of the prior art as discussed above.